1. Field of the Invention
The present invention relates to a memory module, and more particularly to an integrated memory module having memory cells arranged in a matrix and addressable by row and column addresses, in which a plurality of address input terminals are provided for receiving the address signals, an address buffer memory is connected to the input terminals for receiving an address with a row address decoder and a column address decoder for forming row and column selection signals, and in which a data input and a data output are provided.
2. Description of the Prior Art
Integrated memory modules for the construction of write/read memories having random access have respectively undergone a four-fold increase of memory capacity in recent years. At present, 16 Kbit modules are generally available (cf., for example, Memory Data Book and Designers Guide, Mostek Corp., Carollton, Tex., February 1978, pp. 107-122) and 65 Kbit modules are in the testing stage. Also, 262 Kbit modules are under preparation.
All known memory modules of the type under consideration here exhibit a data interface which is 1 bit wide. The length of the addresses increases with the increase in memory capacity. In order to save pins, one has had recourse to subdividing the overall address into two parts in accordance with the internal module row and column address and to input the two parts in succession by way of the same terminal pins. Address acceptance, relaying to the internal address decoder, and activation of internal clock series then occurs by corresponding, chronologically shifted transfer signals.
The increase of the memory capacity of the individual memory modules also produces a considerable reduction of the specific space requirement and of the access time for the memories constructed of such modules. Since, on the other hand, the minimum capacity of a memory with respect to memory words is equal to its capacity in bits because of the 1 bit wide data interface of the memory modules, the continuing increase of the memory capacity of the memory modules of necessity leads to memory sizes which are undesired in many cases such as, for example use thereof in conjunction with microprocessors or as microprogram buffer memories.